Do you have adequate decoupling ? I've had strange wonderful things happen=
=20
before using PLL and bad decoupling caps.

Dom

----- Original Message -----=20
From: "Manu Abraham" <abraham.manu@gmail.com>
To: "Microcontroller discussion list - Public." <piclist@mit.edu>
Sent: Tuesday, February 19, 2013 4:00 PM
Subject: [PIC] Oscillator weirdness ?


> Hi,
>
> I have a dsPIC33FJ16GS502 with a 10MHz xtal as the Primary Oscillator,
> connected between OSC1 and OSC2 along with 2x15pf caps.
>
> While expecting the device to run at 40MIPS, all I see is that RA3
> toggles around 3.3Mhz and 5MHz as can be seen.
>
> RA3 is connected to a LED and Channel 1 of a Logic Sniffer..
>
> http://farm9.staticflickr.com/8515/8489682002_9fcb64b961_b_d.jpg
>
> Any idea why this "jitter" ? Any pointers would be helpful.
>
> The code that toggles RA3 is as follows:
>
> #include <p33fj16gs502.h>
> #include <libpic30.h>
>
>
> _FOSCSEL(FNOSC_PRI)    /* Primary Osc (XT, HS, EC) */
> _FOSC(POSCMD_XT & OSCIOFNC_OFF & FCKSM_CSECMD)    /* XT Osc, OSCO pin
> is CLK out, sw ena, mod disabled */
> _FWDT(FWDTEN_OFF)    /* Watchdog Timer disabled */
> _FPOR(FPWRT_PWR128 & BOREN_OFF)    /* POR Timer 128mS, Brown-out Reset
> disabled */
> _FICD(ICS_PGD3 & JTAGEN_OFF)    /* Use PGC3/EMUC3 and PGD3/EMUD3, JTAG
> Port disabled */
>
>
> void setup_xtosc(void)
> {
>    /* Configure PLL prescaler, PLL postscaler, PLL divisor */
>    PLLFBD =3D 32;
>    CLKDIVbits.PLLPOST =3D 0;    /* N1 =3D 2 */
>    CLKDIVbits.PLLPRE =3D 0;    /* N2 =3D 2 */
>
>    __builtin_write_OSCCONH(0x03);    /* switch to Pri. Osc+PLL=20
> (NOSC=3D0b011) */
>    __builtin_write_OSCCONL(0x01);    /* enable switch */
>
>    while (OSCCONbits.COSC !=3D 0x03); /* wait for clock to switch */
>    while (OSCCONbits.LOCK !=3D 0x01); /* wait for PLL to lock */
>
> }
>
> int main(void)
> {
>    setup_xtosc();
>    TRISA =3D 0;
>
>    while (1) {
>        __builtin_btg((unsigned int *)&LATA, 3); /* toggle RA3 */
>        Nop();
>    }
>    return 0;
> }
>
>
> Thanks,
> Manu
> --=20
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