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Spehro Pefhany <speff@interlog.com> writes:
>><snip>
>>
>>Can anyone think of what I could be doing wrong? Either to get seemingly
>>inconsistent results from a simulator (which I really can't believe
>>actually happened!) or to have such weird behaviour from the chips?
>>
>>Rupert
>
> That data sheet is a bit of a mess, isn't it?  Is SSEL on RA5? Probably
> not, but the data sheet says it is. D110 refers to Vpp on RA5, but I thin=
k
> not.
>
> As a long shot, try clearing APFCON0 APFCON1 and T1CON explicitly
> and clearing bit 5 of the OPTION register.

This doesn't seem to help. Re the OPTION register: Looking at the
datasheet, it seems that TMR0CS (bit 5) only affects whether the T0CKI
pin has an effect on the timer, rather than the pin's configuration
(although I did try it!)

> Personally, I'm not comfortable with leaving registers in their default
> power-up state, and like to set every single relevant one of them explici=
tly
> during the initialization.

You're probably right here.

> You might want to look at the states of all the relevant registers on you=
r
> debugger.

Yep, they come up as the datasheet claims (of course). But the debugger
also thinks everything should work...

Rupert

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