> > >Can anyone think of what I could be doing wrong? Either to get seemingly >inconsistent results from a simulator (which I really can't believe >actually happened!) or to have such weird behaviour from the chips? > >Rupert That data sheet is a bit of a mess, isn't it? Is SSEL on RA5? Probably not, but the data sheet says it is. D110 refers to Vpp on RA5, but I think not. As a long shot, try clearing APFCON0 APFCON1 and T1CON explicitly and clearing bit 5 of the OPTION register. Personally, I'm not comfortable with leaving registers in their default power-up state, and like to set every single relevant one of them explicitl= y during the initialization. You might want to look at the states of all the relevant registers on your debugger. --sp --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .