Oops! I thought the chip driving the FETs was a PIC. I now see it's a gate driver. The gain we're concerned with on Miller effect is the change in drain voltage over the change in gate voltage while the drain voltage is changing (not in saturation or cutoff). During this time, I expect there to be a large drain voltage change with a relatively small gate voltage change. The gate to drain capacitance is multiplied by 1+A where A is this gain to arrive at the apparent gate capacity. I can't zoom in to the schematic well enough to see the gate series resistor values clearly, but I think they are 105 ohms. So, you're only going to get a maximum of 12mA or so as the peak gate current. Perhaps if these resistors were made substantially smaller the circuit would start to behave as you expect. Does the FET gate driver chip have some applications information? I'd expect the series resistor to the gate to be much smaller. Good luck! Harold > Hi, > > > Wouldn't the FET be having a voltage gain=3D1, since the MOSFET driver > also does level shifting ? ie the output of the dsPIC is 5V, but the > IR2110 > is shifting that level to 12V (VB and VCC of the IR2110 are tied to the > same 12V supply), hence for the FET Vo/Vi=3D1 ? > > http://www.flickr.com/photos/79743192@N07/8169359354/in/photostream > The IR2110 can sink about > IO+/- 2A / 2A > =95 Gate drive supply range from 10 to 20V > according to the datasheet: > http://www.irf.com/product-info/datasheets/data/ir2110.pdf > > So, isn't the FET an inverting unity gain buffer ? I think I am missing > something there ? > > Thanks for the help, > > Regards, > Manu > > > On Sat, Nov 10, 2012 at 2:32 AM, Harold Hallikainen > wrote: >> Welcome to the Miller Effect! >> >> The FET is acting as an inverting amplifier. As the gate goes up, the >> drain goes down. There's capacity between the gate and the drain. Let's >> say the voltage gain from the gate to drain is -10. That is, if the gate >> goes up 1V, the drain goes down 10V. >> >> Now, let's say a capacitor to ground, when driven by 1V (for simplicity, >> say it's a sine wave) draws 1A. >> >> Now, connect that same capacitor between the 1V source and the -10V >> source >> (the drain). The capacitor now sees 11V, so it draws 11A. >> >> The gate to source capacity draws 11 times what the capacity to ground >> would draw, so it LOOKS like a capacitor to ground that is 11 times as >> large. >> >> Generalizing, Ci=3D(1+A)C >> >> where Ci is the input capacitance (seen at the gate), A is the voltage >> gain (ignoring sign) from gate to the drain, and C is the capacity from >> the gate to the drain. >> >> Gate capacities are pretty small. But, when multiplied by the voltage >> gain >> of the FET, they become significant. This is why it's common to use gate >> drivers that supply several amps when driving FETs. >> >> If you did not have the transformer in your circuit, but, instead, had >> resistors to positive supply, I'd expect the gate voltage to look >> something like this: >> >> >> >> >> +------------- >> | >> | >> / >> / >> / >> -----------+ >> >> The change from ramp to vertical occurs when the drain voltage hits >> ground. Then the drain voltage is no longer changing at Vin*A, so the >> voltage across Cdg is only the change in Vin, not 1+A times the change >> in >> Vin. >> >> >> Good luck! >> >> Harold >> >> >> >> -- >> FCC Rules Updated Daily at http://www.hallikainen.com - Advertising >> opportunities available! >> Not sent from an iPhone. >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 FCC Rules Updated Daily at http://www.hallikainen.com - Advertising opportunities available! Not sent from an iPhone. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .