Welcome to the Miller Effect!

The FET is acting as an inverting amplifier. As the gate goes up, the
drain goes down. There's capacity between the gate and the drain. Let's
say the voltage gain from the gate to drain is -10. That is, if the gate
goes up 1V, the drain goes down 10V.

Now, let's say a capacitor to ground, when driven by 1V (for simplicity,
say it's a sine wave) draws 1A.

Now, connect that same capacitor between the 1V source and the -10V source
(the drain). The capacitor now sees 11V, so it draws 11A.

The gate to source capacity draws 11 times what the capacity to ground
would draw, so it LOOKS like a capacitor to ground that is 11 times as
large.

Generalizing, Ci=3D(1+A)C

where Ci is the input capacitance (seen at the gate), A is the voltage
gain (ignoring sign) from gate to the drain, and C is the capacity from
the gate to the drain.

Gate capacities are pretty small. But, when multiplied by the voltage gain
of the FET, they become significant. This is why it's common to use gate
drivers that supply several amps when driving FETs.

If you did not have the transformer in your circuit, but, instead, had
resistors to positive supply, I'd expect the gate voltage to look
something like this:




              +-------------
              |
              |
             /
            /
           /
-----------+

The change from ramp to vertical occurs when the drain voltage hits
ground. Then the drain voltage is no longer changing at Vin*A, so the
voltage across Cdg is only the change in Vin, not 1+A times the change in
Vin.


Good luck!

Harold



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