> -----Original Message-----
> From: piclist-bounces@MIT.EDU [mailto:piclist-bounces@MIT.EDU] On
> Behalf Of Spehro Pefhany
> Sent: 24 October 2012 23:22
> To: Microcontroller discussion list - Public.
> Subject: Re: [EE] I2C slew rate limiting
>=20
> At 03:35 PM 10/24/2012, you wrote:
> >Mark Rages wrote:
> > > On Wed, Oct 24, 2012 at 10:26 AM, Michael Rigby-Jones
> > > <Michael.Rigby-Jones@oclaro.com> wrote:
> > >
> > >> Does anyone know of a technique (e.g. IC or simple discrete
> > circuit) to limit the slew rate on the falling edge of I2C clock and
> > data, without significantly raising the zero voltage level (as a
> > simple RC circuit would)?
> > >>
> > >
> > > Well, you select "R" and "C" to get the rise times you want, and
> > > only "R" affects the noise margin.  So big "C", little "R"?
> > >
> >The trouble is on an open collector bus like i2c the rise time is
> >naturally much slower than the fall time. AIUI he wants to increase the
> >fall time without increasing the rise time too much.
> >
> >IMO a LC circuit is probablly the way to go.
>=20
> LC could cause ringing-- the Q will be much higher on the down edges.
>=20
> I think I'd look carefully at a bus repeater with active slew rate contro=
l such as
> the NXP PCA9509A.

Thanks Sphero, that's exactly the sort of thing I wanted, and it comes in a=
 nice small QFN package which is ideal.

Another engineer has actually had some success using an LC filter with lots=
 of damping to pretty much eliminate the ringing, but active slew control s=
eems like a better way to go than brute force methods.

Cheers

Mike

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