At 03:35 PM 10/24/2012, you wrote:
>Mark Rages wrote:
> > On Wed, Oct 24, 2012 at 10:26 AM, Michael Rigby-Jones
> > <Michael.Rigby-Jones@oclaro.com> wrote:
> >
> >> Does anyone know of a technique (e.g. IC or simple discrete=20
> circuit) to limit the slew rate on the falling edge of I2C clock=20
> and data, without significantly raising the zero voltage level (as=20
> a simple RC circuit would)?
> >>
> >
> > Well, you select "R" and "C" to get the rise times you want, and only
> > "R" affects the noise margin.  So big "C", little "R"?
> >
>The trouble is on an open collector bus like i2c the rise time is
>naturally much slower
>than the fall time. AIUI he wants to increase the fall time without
>increasing the rise time
>too much.
>
>IMO a LC circuit is probablly the way to go.

LC could cause ringing-- the Q will be much higher on the down edges.

I think I'd look carefully at a bus repeater with active slew rate=20
control such as the NXP
PCA9509A.

Bset regards,


--=20
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