Mark Rages wrote:
> On Wed, Oct 24, 2012 at 10:26 AM, Michael Rigby-Jones
> <Michael.Rigby-Jones@oclaro.com> wrote:
>  =20
>> Does anyone know of a technique (e.g. IC or simple discrete circuit) to =
limit the slew rate on the falling edge of I2C clock and data, without sign=
ificantly raising the zero voltage level (as a simple RC circuit would)?
>>    =20
>
> Well, you select "R" and "C" to get the rise times you want, and only
> "R" affects the noise margin.  So big "C", little "R"?
>  =20
The trouble is on an open collector bus like i2c the rise time is=20
naturally much slower
than the fall time. AIUI he wants to increase the fall time without=20
increasing the rise time
too much.

IMO a LC circuit is probablly the way to go.
--=20
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