Michael Rigby-Jones wrote:
> Does anyone know of a technique (e.g. IC or simple discrete circuit) to
> limit the slew rate on the falling edge of I2C clock and data, without
> significantly raising the zero voltage level (as a simple RC circuit woul=
d)?
>=20
> The background is I have an application specific mixed signal device (i.e=
..
> not something I can simply get from another vendor) that shows significan=
t
> clock/data breakthrough from the I2C bus to the analog sections. Slowing
> the falling edge helps greatly (suggesting capacitive coupling with the
> device is to blame), but a simple RC network on the data/clock lines not
> only has a big impact on the rising edge speed, but also forms a potentia=
l
> divider with the bus pull-up resistors and raises the logic zero voltage.
> Results so far have been achieved by juggling pull-up and RC filter value=
s
> to prove the idea, but the noise immunity at the zero level has been
> significantly degraded and rise time exceeds the device spec (though it
> still works).
>=20
> Obviously this can only work for write from the master to the slave, sinc=
e
> I have no way of controlling the slew rate of the data line within the AS=
IC
> when it's pulling the data line low. Fortunately the vast majority of the
> traffic is a write from master to slave, so this is not a show stopper.

I would be tempted to try putting some SMT ferrite beads at the pins of the
CPU's I2C interface. This should slow down the falling edges on the bus
without introducing significant DC offsets.

I wouldn't put one at the SDA pin of the slave, however. While this would
reduce the speed of the falling data edges, it would also *increase* the sp=
eed
of the rising edge at the device's pin when its driver shuts off, which wou=
ld
probably be counterproductive.

-- Dave Tweed
--=20
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