Does anyone know of a technique (e.g. IC or simple discrete circuit) to lim=
it the slew rate on the falling edge of I2C clock and data, without signifi=
cantly raising the zero voltage level (as a simple RC circuit would)?

The background is I have an application specific mixed signal device (i.e. =
not something I can simply get from another vendor) that shows significant =
clock/data breakthrough from the I2C bus to the analog sections.  Slowing t=
he falling edge helps greatly (suggesting capacitive coupling with the devi=
ce is to blame), but a simple RC network on the data/clock lines not only h=
as a big impact on the rising edge speed, but also forms a potential divide=
r with the bus pull-up resistors and raises the logic zero voltage.  Result=
s so far have been achieved by juggling pull-up and RC filter values to pro=
ve the idea, but the noise immunity at the zero level has been significantl=
y degraded and rise time exceeds the device spec (though it still works).

Obviously this can only work for write from the master to the slave, since =
I have no way of controlling the slew rate of the data line within the ASIC=
 when it's pulling the data line low.  Fortunately the vast majority of the=
 traffic is a write from master to slave, so this is not a show stopper.

Thanks

Mike

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