Yep...the PCB designs are very complex, when your doing a 3TB drive on PCIe= :-) Big FPGAs with ODP NAND's but it does get you there. How many applications are there that really need more than 64GB of ram and = yet don't also need a correspondingly crazy ammount of CPU. > There have long been FPGAs with built-in DDR3 controllers as well as=20 > PCI-e controllers. To build a similar device, for example, something=20 > with multiple slots that can address more than 256GB of RAM would be nice= .. > > How expensive and difficult would this be? Most of the logic is=20 > already there, the only thing really is the electrical engineering=20 > (routing, layout, etc.) considerations and the memory addressing logic=20 > which doesn't seem too hard from what I know (I've built a simple=20 > memory controller on a Spartan 3E for my PIC32 in the past). The problem is that both the speeds and the number of lines involved are ve= ry large. For signal integrity reasons with modern memory modules you don't= really want to be putting more than two modules per channel and each chann= el is going to have a lot of lines (the data bus along is 128 bits wide on = PC memory modules). That makes the PCB design decidedly difficult and a lot of layers will be n= eeded. That combined with the big BGAs means that prototyping costs will be very h= igh. -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membershi= p options at http://mailman.mit.edu/mailman/listinfo/piclist This e-mail (and any attachments) is confidential and may be privileged. A= ny unauthorized use, copying, disclosure or dissemination of this communica= tion is prohibited. If you are not the intended recipient, please notify = the sender immediately and delete all copies of the message and its attachm= ents. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .