I always use the recommended one-capacitor-per-pin-pair plus one bulk capacitor for each big chip or group of chips (usually 10uF ceramic) and never had any problems. Once I designed a DM9191AEP Ethernet PHY sub-circuit and forgot three 100nF capacitors. The circuit ended up without any decoupling near the chip's three digital power pins. There were decoupling capacitors for the analog power rails of the chip and for other nearby sub-circuits. The circuit worked OK until I did a copy-and-paste design (copied the entire DM9191AEP Ethernet PHY sub-circuit from one design to another). The new design was much smaller, with the DM9161AEP being one of the only two chips on the board and with much less decoupling spread over the board. This time it worked intermittently. After the analysis of the new design I found an undetected error on the first design. Isaac Em 2/9/2012 03:30, Chetan Bhargava escreveu: > My original question was about practical designs. How many of you > manage to put 4x de-caps on 4x set of power pins of a TQFP > microcontroller (PIC)? > I managed to put 3x caps (1x on same layer with PIC and 2x on bottom > layer with vias). Would this be close to best practices? > > Thanks > > Chetan Bhargava > http://microz.blogspot.com > > > On Sat, Sep 1, 2012 at 10:40 PM, Chetan Bhargava wr= ote: >> My design is a power controller that delivers ~10x power rails to a >> high speed serial memory IC. The serial PHY is 10GHz Ser-Des and the >> ripple tolerances are pretty low (10mv p-p max). This chip works with >> Altera and Xilinx FPGAs hence similar design considerations. >> >> I can very well understand the coupling requirements. >> >> Thanks >> >> Chetan Bhargava >> http://microz.blogspot.com >> >> >> On Sat, Sep 1, 2012 at 10:23 PM, Harold Hallikainen >> wrote: >>> I've generally put them "as close as possible" and had no problems. But= , >>> that's not very specific. >>> >>> I did some analysis on bypass capacitors for a couple Altera FPGAs. The= y >>> have a nice spreadsheet that takes a LOT into consideration. It takes t= he >>> ripple current on the pin and the allowed ripple voltage, then determin= es >>> the maximum impedance allowed. It then looks at the impedance of the >>> capacitor, the impedance of traces to the capacitors, impedance of vias= , >>> parallel capacity of power planes, and internal bypassing for very high >>> frequencies. It's very thorough. But, I haven't seen anything like that >>> for a PIC. >>> >>> Harold --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .