My original question was about practical designs. How many of you manage to put 4x de-caps on 4x set of power pins of a TQFP microcontroller (PIC)? I managed to put 3x caps (1x on same layer with PIC and 2x on bottom layer with vias). Would this be close to best practices? Thanks Chetan Bhargava http://microz.blogspot.com On Sat, Sep 1, 2012 at 10:40 PM, Chetan Bhargava wrot= e: > My design is a power controller that delivers ~10x power rails to a > high speed serial memory IC. The serial PHY is 10GHz Ser-Des and the > ripple tolerances are pretty low (10mv p-p max). This chip works with > Altera and Xilinx FPGAs hence similar design considerations. > > I can very well understand the coupling requirements. > > Thanks > > Chetan Bhargava > http://microz.blogspot.com > > > On Sat, Sep 1, 2012 at 10:23 PM, Harold Hallikainen > wrote: >> I've generally put them "as close as possible" and had no problems. But, >> that's not very specific. >> >> I did some analysis on bypass capacitors for a couple Altera FPGAs. They >> have a nice spreadsheet that takes a LOT into consideration. It takes th= e >> ripple current on the pin and the allowed ripple voltage, then determine= s >> the maximum impedance allowed. It then looks at the impedance of the >> capacitor, the impedance of traces to the capacitors, impedance of vias, >> parallel capacity of power planes, and internal bypassing for very high >> frequencies. It's very thorough. But, I haven't seen anything like that >> for a PIC. >> >> Harold --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .