My design is a power controller that delivers ~10x power rails to a
high speed serial memory IC. The serial PHY is 10GHz Ser-Des and the
ripple tolerances are pretty low (10mv p-p max). This chip works with
Altera and Xilinx FPGAs hence similar design considerations.

I can very well understand the coupling requirements.

Thanks

Chetan Bhargava
http://microz.blogspot.com


On Sat, Sep 1, 2012 at 10:23 PM, Harold Hallikainen
<harold@hallikainen.org> wrote:
> I've generally put them "as close as possible" and had no problems. But,
> that's not very specific.
>
> I did some analysis on bypass capacitors for a couple Altera FPGAs. They
> have a nice spreadsheet that takes a LOT into consideration. It takes the
> ripple current on the pin and the allowed ripple voltage, then determines
> the maximum impedance allowed. It then looks at the impedance of the
> capacitor, the impedance of traces to the capacitors, impedance of vias,
> parallel capacity of power planes, and internal bypassing for very high
> frequencies. It's very thorough. But, I haven't seen anything like that
> for a PIC.
>
> Harold
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