On 25 August 2012 02:40, Jan-Erik Soderholm <jan-erik.soderholm@telia.com>w=
rote:

> The first case (capactive loading) is hard (if not impossible)
> to simulate using something like MPSIM.
>

I have to disagree with that, already explained that a simple time stamp on
the port would do that for you. So you store the actual time tick when the
port was written, then next time you do an RMW instruction it checks if at
least 4 ticks (or any other configurable value) passed since. Knowing the
simulated fosc frequency you may even could setup the constrain of
simulated time instead of the ticks.

Also a compiler could detect RMW instructions right after each others and
display a warning, that's not a rocket science either.

With this latter one maybe Microchip could provide a kind of static
analysis tool such as lint or splint, which would help us detecting obvious
mistakes or bogus code...

http://en.wikipedia.org/wiki/List_of_tools_for_static_code_analysis

Tamas




>
> Jan-Erik.
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> >
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printf(s=3D%s%s%s, q=3D%s%s%s%s,s,q,q,a=3D%s%s%s%s,q,q,q,a,a,q); }",
q=3D"\"",s,q,q,a=3D"\\",q,q,q,a,a,q); }
--=20
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