On Tue, August 21, 2012 12:06 pm, Bob Blick wrote:
> On Tue, Aug 21, 2012, at 09:59 AM, Jason White wrote:
>> > Is that really optional? I can't think of any upside for leaving it
>> out.
>> > I welcome any thoughts on it.
>> >
>> > Thanks,
>> > Bob
>>
>> Wouldn't it free up space for routing traces beneath the chip ?
>
> Only if I used tented vias (filled with resist). I don't like having
> bare vias under conductors. And even if I spec tented vias, quite often
> that gets changed in later production runs (another story, arghh!).
>
> Thanks!
>
> Bob
>

The option is if you use it or not, but you should expect it to be there.
That pad is a remnant of the package- DFNs and QFNs were originally
designed for higher power applications, but the package is nice and small,
so many companies choose to use it in applications that don't need the
lower thermal resistance of the package. Removing it would make it a
non-standard package and probably cause many more problems than it would
be worth as many (all?) solder stencil patterns will have it there.

The real answer is: don't route under QFN packages.

Matt Bennett
Just outside of Austin, TX
30.51,-97.91

The views I express are my own, not that of my employer, a large
multinational corporation that you are familiar with.
--=20
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