On Wed, Aug 15, 2012 at 11:07 AM, Spehro Pefhany <speff@interlog.com> wrote=
:
> At 08:05 AM 15/08/2012, you wrote:
>>I'm out of my element when it comes to practical PLL circuits.
>>I'm considering using a PLL to create a 25MHz signal which should be
>>phase locked to an input reference 20MHz signal. Do you know of some
>>ICs that I could consider for this purpose?
>>Most of the ones that I have seen quote significantly higher frequency
>>values. Usually higher than 200 MHz.
>
> TI 74HC4046/7046 will run at 25MHz (5V supply), but it's close to
> the top. You have to be a bit careful with the '4046 series- they can var=
y
> a LOT from manufacturer to manufacturer.
>
> There are also clock distribution etc. chips that should do the whole thi=
ng
> (programmable dividers etc). CDE906, and there are many others. Most tend=
 to
> be very power-hungry, IME, if that's a concern for you.
>
> A Pericom PI6C4511 set to x2.5 followed by a divide-by-two (eg. SN74LVC1G=
175)
> from 50MHz down to 25MHz might be the simplest solution (no programming
> required, and relatively reasonable current draw from either 3.3V or 5V).
> The divide-by-two ensures 50:50 duty cycle too, if that's a concern.


Thank you everyone for the recommendations.
I think Spehro's recommendation of the PI6C4511 fits well with my applicati=
on.

For those interested, this is a 20 MHz reference clock from a Zygo
interferometer laser head. Our lab has an RF generator that is
synchronized to this reference, for debugging purposes.
The RF generator (one version of it) requires a 25 MHz signal.
http://snl.mit.edu/papers/papers/2002/cc_SPIE2002.pdf


--=20
Martin K.
--=20
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