In past devices I've saved a pin and sitll used /CS by pulling it low with
a diode to clk, and a R pullup and C that raises /CS after about 4 clock
periods. I set clock pol/pha to keep clk high after a transaction,
but still provide rising edges to clock in the data.
Most devices are ok with slightly sloppy /CS rise time. If not, square it
up with a couple of SOT23 74HC14 devices.

R

On Wed, Aug 15, 2012 at 9:22 AM, Michael Rigby-Jones <
Michael.Rigby-Jones@oclaro.com> wrote:

> On Tue, Aug 14, 2012 at 8:39 PM, Harold Hallikainen <
> harold@hallikainen.org> wrote:
> >>
> >> I've heard of this being done, but I've always wondered how you tell
> >> which bit is which. With CSn, the msb is clearly the first bit after
> >> CSn goes low. If CSn is always low, how do you know which bit is which=
?
> >>
> >> Harold
> >>
>
> >-----Original Message-----
> >From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf
> Of Chetan Bhargava
> >Sent: 15 August 2012 16:01
> >To: Microcontroller discussion list - Public.
> >Subject: Re: [EE] SPI OLED CS signal
> >
> >Data and clock pair are independent of CS. You keep the data clocking
> >routine the same irrespective of CD connected to micro or tied low.
> >
> >Chetan Bhargava
>
> You may be able to do this as long as the SPI slave device does not rely
> on the rising edge of the CS pin to load any internal registers (many/mos=
t
> SPI peripherals do).  However, the downside is that a single glitch on th=
e
> clock line will irretrievably lose the synchronisation between the slave
> and the master.
>
> Regards
>
> Mike
>
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