On Sun, 10 Jun 2012 11:46:24 -0700 (PDT), Andre Abelian wrote:

> ...
>
> I noticed that altera uses external ic to hold the program memory is
> there any advantage?
> ?why use external some one can still the code. ?how come xilinx or
> lattice program memory is internal.
>
> ...

Most FPGAs load their bitstream from an external source (ie.
non-volatile memory, JTAG controller, a microcontroller, etc.) as they
lose configuration when power drops below a given threshold (ie. turned
off).

Out of these options, it tends to be Flash based memory for lower cost
devices, since they're cheap (ie. about 60p in singles for a W25Q16CV
16Mbit SPI device) - SD cards also tend to be incompatible, too
(although I dare say there are devices out there capable of loading
directly off them).  For example, the Xilinx Spartan 6 initial clock
rate for configuration is about 1MHz, higher than the SD card
interface's initial (pre-negotiation) 400kHz clock requirement.

There are some technologies (eFuse I believe Xilinx call it) that allow
you to stick the bitstream internal to the device, but these tend to be
higher-end devices.  These same devices also tend to have battery
backups to store AES keys and encrypted bitstreams, too.  That handles
the IP theft to an extent - all (encrypted) IP is inside the device, and
the AES key / decrypted bitstream is non-readable by any of the loaded
firmware.

As for the technical (or historical ?) reasons behind FPGA volatility
vs. CPLD non-volatility, I have no idea - that would be enlightening if
somebody in the know could comment on it.

Hope this helps.

Regards,

Pete Restall
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