Mark, good info.. thanks AA ________________________________ From: Mark Hanchey To: piclist@mit.edu=20 Sent: Monday, June 11, 2012 4:45 AM Subject: Re: [EE]: FPGA external program memory =20 On 6/11/2012 2:23 AM, William "Chops" Westfield wrote: > It was FPGA security features recently that were recently cracked,=20 > BTW. Basically, it seems that certain features were protected by=20 > locking them under a key (AES128 - nothing to sneeze at.) While this=20 > potentially means that the manufacturer had a back door to the=20 > commands, the big problem turned out to be that keys were "pretty=20 > easy" to extract from the chip via "side-channel attacks."=20 http://erratasec.blogspot.com/2012/05/bogus-story-no-chinese-backdoor-in.ht= ml=20 BillW http://www.altera.com/devices/fpga/cyclone3/overview/security/cy3-security.= html It was a bad design to start with to allow programming accessible via=20 jtag. That is why I like chips like the Cyclone III LS , the security=20 part of the chip isn't accessible via jtag at all, it is constantly=20 monitoring the traffic of the jtag bus and=A0 at the first sign of=20 tampering it can be set to zero the device so that it gets really=20 expensive to keep trying to hack the protection. Mark --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .