Neil wrote 2012-06-07 21:04:
>>
>> Curious -- if some high-priority interrupt code is being processed and
>> before it completes 2 low-priority interrupts are triggered, is there a
>> defined order in which those get processed when the high-priority
>> interrupt completes?  I suspect the PIC looks for these in some
>> hard-coded order, or perhaps it would know which got triggered first,
>> but I've not seen anything in the datasheet that indicates that either
>> of these is true.
>>

No, the PIC does not keep track on in which order the different
*IF flags are set. As soon as the ISR can be called, one or many
IF-flags *could* have been set. The ISR is a fixed address anyway
(for each prio) and it is up to the ISR to put a priority on how
the different sources are services (by the order the different
*IF flags are checked in the ISR).

The only "order" is the configurable high/low prio (if used).

And the PIC doesn't realy "look" for anything, this is hardwired
traditional logic, not some internal (sequencial) code. The
different interrupt sources are simply OR'ed together, more
or less.

Jan-Erik.






>> Cheers,
>> -Neil
>>
>>
>>
>> On 6/5/2012 3:44 PM, Brendan Gillatt wrote:
>>> 18F chips have a dual-priority interrupt system. Try using that before
>>> doing loops, etc. Set you're overflow ISR as high priority and
>>> everything else as 'standard' priority. (Also, the high priority ISR
>>> automatically saves context on interrupt entry and exit IIRC). Low
>>> priority ISRs can be interrupted by high priority ISRs but not the
>>> other way around. All the best
>
--=20
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