It gets worse -- I put all 3 other timers as low-priority, so the=20
32.768khz osc is the only remaining high-priority interrupt, and time is=20
still moving fast.  Now I'm lost... and desperate to figure this out.



On 6/7/2012 2:20 PM, Neil wrote:
> I have priorities in use, with 1 timer as low priority and 3 timers as
> high.  The multiplexed display updates are usually high as I get a
> slight flicker on the display otherwise, but now that I'm running at
> 32Mhz, I've set it to low priority and it seems to be fine.  I'm
> retesting the clock now, but if that issue is still not resolved, I have
> one other option...
>
> Other than the 32.768khz osc, the only other high-priority timer now is
> the one that samples a bit for a frequency measurement.  That code is
> relatively bulky (for an ISR), so I suspect it will have to change
> somehow.  I'm thinking I'll need to come up with some way to sample the
> bit at the correct time and store it.  Either store in a queue for later
> processing in main code, or store a single bit sample and force trigger
> a low-priority interrupt for relatively immediate processing.  For the
> latter, I'm guessing I can just force on the interrupt flag for some
> interrupt I'm not using (another timer, etc).
>
> Curious -- if some high-priority interrupt code is being processed and
> before it completes 2 low-priority interrupts are triggered, is there a
> defined order in which those get processed when the high-priority
> interrupt completes?  I suspect the PIC looks for these in some
> hard-coded order, or perhaps it would know which got triggered first,
> but I've not seen anything in the datasheet that indicates that either
> of these is true.
>
> Cheers,
> -Neil
>
>
>
> On 6/5/2012 3:44 PM, Brendan Gillatt wrote:
>> 18F chips have a dual-priority interrupt system. Try using that before
>> doing loops, etc. Set you're overflow ISR as high priority and
>> everything else as 'standard' priority. (Also, the high priority ISR
>> automatically saves context on interrupt entry and exit IIRC). Low
>> priority ISRs can be interrupted by high priority ISRs but not the
>> other way around. All the best

--=20
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