I have priorities in use, with 1 timer as low priority and 3 timers as=20
high.  The multiplexed display updates are usually high as I get a=20
slight flicker on the display otherwise, but now that I'm running at=20
32Mhz, I've set it to low priority and it seems to be fine.  I'm=20
retesting the clock now, but if that issue is still not resolved, I have=20
one other option...

Other than the 32.768khz osc, the only other high-priority timer now is=20
the one that samples a bit for a frequency measurement.  That code is=20
relatively bulky (for an ISR), so I suspect it will have to change=20
somehow.  I'm thinking I'll need to come up with some way to sample the=20
bit at the correct time and store it.  Either store in a queue for later=20
processing in main code, or store a single bit sample and force trigger=20
a low-priority interrupt for relatively immediate processing.  For the=20
latter, I'm guessing I can just force on the interrupt flag for some=20
interrupt I'm not using (another timer, etc).

Curious -- if some high-priority interrupt code is being processed and=20
before it completes 2 low-priority interrupts are triggered, is there a=20
defined order in which those get processed when the high-priority=20
interrupt completes?  I suspect the PIC looks for these in some=20
hard-coded order, or perhaps it would know which got triggered first,=20
but I've not seen anything in the datasheet that indicates that either=20
of these is true.

Cheers,
-Neil



On 6/5/2012 3:44 PM, Brendan Gillatt wrote:
> 18F chips have a dual-priority interrupt system. Try using that before=20
> doing loops, etc. Set you're overflow ISR as high priority and=20
> everything else as 'standard' priority. (Also, the high priority ISR=20
> automatically saves context on interrupt entry and exit IIRC). Low=20
> priority ISRs can be interrupted by high priority ISRs but not the=20
> other way around. All the best=20

--=20
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