Hi!Thank you everybody for your replies.The circuit has to be simple,and easily adjusted in the field.The output is a tone in the audio speech range,suitable for radio or landline transmission.The freq is critical,and the pic reads this at the base.To generate the tone,a 4060 is to be used, and the oscillator will be able to use small value,stable cap and a resistor (multiturn trimpot).Original plan was to generate a square wave at the desired freq. at the end of the counter chain .I had hoped to use a higher starting oscillator freq and R-2R network to generate a sine wave.Thoughts are now to do this for the rising half wave,use the output of the next stage of the counter to isolate the counter output for the falling half, and have a capacitor (that charged up during the rising half) discharge to give a rough output for the falling half. Very rough,but still better than just the square wave.It is important a tech with a multimeter can check and adjust the freq in the field,and a lot of multimeters have built in freq reading ability.The problem is I am trying to kludge a down counter for the falling half of the sinewave! On Fri, May 18, 2012 at 2:23 AM, Spehro Pefhany wrote: > At 05:44 AM 17/05/2012, you wrote: > >Tag added, PIC, in case it veers that way > > The classic way to do this is with a Johnson counter. See > AoE figure 9.93 for an implementation using a 4015 > and an inverter that yields a 16-level approximation to a > sine wave. > > >Off the top of my head, once the output of the counter passes 111 > >or 1111, the next o/p bit should toggle inverting logic > > > >I think 4 x XOR gates should do it. Each bit of low-order data from > >the counter goes to an A input, the logic control bit is commoned to > >the B inputs > > > >FYI - > > > >Attached is a circuit I use to make a variable AC voltage. The ADC > >pot changes the period of a timer. Output is a fairly good sine wave. > >Filter components depend on the frequency range for best output, > >although a constant-amplification amplifier could be added. My range > >for this circuit is quite low, 5 - 50Hz > > > >Joe > > Trivial to do with a PIC. Just generate an interrupt, spit > out the new number, increment the pointer to your table > modulo 256 (say), look up the next number, and set your > comparator for the next interrupt. Your interrupts will be > at your sine wave frequency * 256, so with a 200ns timer > resolution you'll get a resolution of about 0.25Hz at 50Hz. > PICs (at least the smaller ones) have constant interrupt > latency so this is feasible without extra parts or jitter. > If there was variable latency and the jitter was excessive, > you could make a pin toggle right at the comparator hit > and clock an external buffer (pipelined, obviously). Another > part. If I had to that, I'd probably use an HC595 and > use a serial output from the PIC (the 595 is a serial-to- > parallel SR with an edge-triggered output buffer). > > There are other techniques (phase accumulator) that can be > used to improve resolution with a relatively modest clock > rate (at the expense of more complexity and some jitter), > but maybe you don't need to do that. > > Best regards, > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .