Great thread and response.  Thank you David yet again for sharing your=20
experience.  I'm entering the world for FCC part 15 compliance for all=20
new designs and tips like this are invaluable.

J


David VanHorn wrote:
>>         But the thing is, in any pictures I've found online of PIC-based
>> PCBs, no-one seems to actually be doing this isolating "ring".  So is
>> it really something I should be concerning myself with?  Or ideally,
>> does anyone know a way of geting multiple "GND"-named polygons on a
>> layer in Eagle?
>
> I don't run Eagle, but I can answer the question on the why of it.
>
> The crystal load caps should be returned only, and directly, to the
> ground pin on the CPU nearest the oscillator pins. That pin should be
> the only point where the crystal system touches the rest of the
> ground. Otherwise, you are allowing oscillator currents (at the
> fundamental and all harmonics) to flow into your plane and they will
> radiate.  This is also a door that opens both ways. The oscillator
> done improperly is more prone to being upset by externally applied
> fields and other currents flowing in the rest of the ground system.
>
> This is the right way to do it, whether or not other people do it that
> way.  Ask those guys if their designs pass part 15 first time, every
> time, and in fact are barely above the noise floor of the analyzer
> instead of barely below the fail line.
>
>
> Think of it this way.  It isn't strictly true that current always
> takes the shortest path.  It actually takes every possible path, it
> just prefers the short one.   If you want quiet PCBs, return current
> to where you got it from, by low impedance direct traces.
>
> Also, the caps are in series and will need to be a bit less than twice
> the specified Cl value, another one that is commonly done wrong but
> usually "works".
>
> :)
>
> As to how to do that in eagle, can you place a "keep out" that the
> flood will respect?
>
--=20
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