>> http://dl.dropbox.com/u/13600361/BAT%2BMOS.png
>
> thanks!
>
> As I see it this uses the FET to conduct in revers mode (D is positive
> with regards to S), correct? I don't see information (RDson figures) for
> this mode in the datasheets that I looked in. Is it safe to assume that
> the D and S behave symmetrical?

Yes assume that for Rds.




>
> R72 keeps the gate low when there is no +5V, which makes the FET
> conduct. When +5V is available, the gate is more positive than D or S,
> so the FET is open.
>
> But what is R68 for? It halves the gate voltage in the battery-only
> mode, which seems a bad idea?


Picture that there is no power source other than battery.

Taking out R68 and at initial power-up, Source would be 0.7V less than
Drain. hence, Bat=3D3V, VDD=3D2.3V
Immediately FET will close because Vgs beyond threshold. Hence
VDD=3Dwee-bit-less-BAT.

R68 was there because of Vgs max voltages... anyway, copypaste from
other circuits.
It may be ommited if you like.
--=20
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