> http://dl.dropbox.com/u/13600361/BAT%2BMOS.png

thanks!

As I see it this uses the FET to conduct in revers mode (D is positive=20
with regards to S), correct? I don't see information (RDson figures) for=20
this mode in the datasheets that I looked in. Is it safe to assume that=20
the D and S behave symmetrical?

R72 keeps the gate low when there is no +5V, which makes the FET=20
conduct. When +5V is available, the gate is more positive than D or S,=20
so the FET is open.

But what is R68 for? It halves the gate voltage in the battery-only=20
mode, which seems a bad idea?

--=20

Wouter van Ooijen

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--=20
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