> > The new NXP LPC18xx =A0devices use large RAM and booting from external =
SPI flash to
> get 180MHz.
>=20
> I'm not familiar with the LPC18xx series but that sounds interesting.
> The STM32F4 line uses a fairly simple and modest sized cache called an AR=
T to
> improve speed to around those levels.
>=20
> >>The Broadcom behemoth on the R-Pi will have a nice big chunk of fast,
> >>SRAM cache from which it pulls its instructions from, avoiding the
> >>bottle-neck when accessing non-volatile memory.

Note that the RP will be essentially running from RAM once it has booted, a=
s the only bulk non-volatile storage is an SD card, and you wouldn't want t=
o be running such a device on a 4 bit wide ROM bus ...


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