> I remembered this differently so I just had to go take a look. Seems
> you're right. I thought this RISC processor executed 1 instruction per CP=
U
> cycle (maybe 2 cycles depending on memory access). Turns out it can take
> several cycles depending on the specific instruction.

Be careful: a pipelined processor (which the ARM9 is) will take several=20
clock cycles to complete an instruction (from staring the instruction to=20
completing it), but can (at full speed) complete one instruction each=20
clock cycle! (because each stage of the pipeline can be working on a=20
different instruction)

--=20

Wouter van Ooijen

-- -------------------------------------------
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docent Hogeschool van Utrecht: www.voti.nl/hvu
C++ on uC blog: http://www.voti.nl/erblog

--=20
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