On Thu, Feb 16, 2012 at 8:07 PM, Vasile Surducan wrote= : > On Thu, Feb 16, 2012 at 5:15 PM, Dave Tweed wrote: >> Vasile Surducan wrote: >>> On Thu, Feb 16, 2012 at 2:50 PM, =A0 wrote: >>> > > > Hi all, >>> > > > >>> > > > I need to interface an 120Msps serial ADC with LVDS output to an = USB >>> > > > 2.0. Does anyone knows a small ASIC, DSP or whatever which allows= this >>> > > > simple task. I thought also to USB to SATA bridge, however I need= a >>> > > > few programmable IOs for controlling the A2D, >>> > > >>> > > Classic application for a small FPGA, plus FTDI FTx232H hi-speed US= B >>> > > interface. FPGA will handle LVDS conversion, some RAM for buffering= and >>> > > handshaking. >>> > >>> > When you say LVDS, what format is it? Does it work just like an SPI d= evice >>> > (LVDS really is only the differential hardware layer). If it does wor= k >>> > like an SPI device then a Microchip 2210 USB-SPI with an LVDS driver = and >>> > receiver chip may do what you want. >>> >>> It's 14 bit serial output in one lane (one bit a time) or two lane >>> (two bits at a time) and frame, all LVDS output. >>> Also has a SPI for commands. See for example LTC2268. >> >> Clearly, this is anything but a "simple task". Given that high-speed USB= can >> only support about 40 MBps sustained, you'd only be able to operate this= chip >> at 20 Msps or so with a "bare-bones" interface. If you want to burst dat= a at >> higher sample rates, you're going to need a significant amount of high-s= peed >> buffer memory between the ADC and the USB. >> >> Just as an example, look at Linear's DC1371A board, which performs the >> function you are asking for. It includes a rather hefty Virtex-5 FPGA al= ong >> with a couple of high-speed ZBT SRAMs. Granted, this board supports many= more >> features than you probably need, but the basic data handling is going to= be >> very similar. >> >> You're going to have to give us a better idea of what you're trying to d= o with >> this chip before we can offer meaningful suggestions. BTW, this is exact= ly the >> sort of FPGA design work that I do. If you'd like to discuss this projec= t >> off-list, send a message to dtweed at dtweed dot com. > > Thx Dave, > I know quite well Virtex5, I've designed one project with, but now is > not applicable because of space and power constraint. In fact Virtex5 > is good only if an ASIC is finally implemented, which is not the case. > I think the price of Virtex5 does not recommend it for such > application. So, USB2.0 can only 40Mbps? OK, 40MBps, that's correct. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .