You're welcome! At 20.52 2012.02.09, you wrote: >Thanks for sharing. > >2012/2/9 Electron > >> PS: no, the compiler is behaving correctly, it must be an hardware issue= .. >> >> Specifically this looks like trouble: >> >> sw a1,-28672(v1) ; SAMP=3D1 >> loop: lw v1,-28672(a2) ; while (!AD1CON1bits.DONE); >> andi v1,v1,0x1 >> beq v1,zero,loop >> >> insert a nop between the first and second instructions, and the bug is >> gone. >> >> I was aware of such issues only when writing '0' to the ON bit of a modu= le, >> in fact every time I disable a module, I add a nop. But I wasn't aware (= and >> the documentation would exclude it) that a store immediately followed by= a >> load from the same register would cause corruption, or maybe it's just t= he >> ADC module that (sometimes!) doesn't have enough time to clear DONE afte= r >> SAMP is set. >> >> Please note that PB=3D1 of course (peripheral bus clock is same as CPU >> clock). >> >> In any case, that wasted 5 hours of my life.. and bughunting is not real= ly >> my favourite sport, but every such situation has something to teach.. an= d I >> wanted to share this with you all ADC-weirdly-behaving frustrated fellow= s. >> >> With kind regards, >> Mario >> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> >--=20 >http://www.piclist.com PIC/SX FAQ & list archive >View/change your membership options at >http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .