Dear Chris, At 00.14 2012.02.05, you wrote: >You may find this page useful: > >http://www.chipkit.org/wiki/index.php?title=3DCore_Function_Overview > >It is related to how the ChipKit uses the Core Timer but has some >interesting comments about using it in general. Thanks, however I have the core timer working perfectly, the problem (not just of the core timer, but of any interrupt) is if I go level 7.. all othe= r levels work great. It's clearly a shadow register set issue, maybe a bug of this compiler version which just added support for the device (PIC32MX1XX) I am using. By the way, in the link You posted above, point 2 is wrong: 2.Do not do anything that could cause the CoreTimerHandler ISR to be called= recursively. Primarily, this means do not enable interrupts as the core ti= mer interrupt flag is still set and will immediately cause the system to ca= ll CoreTimerHandler ISR recursively.=20 This cannot happen, as if You enable (EI) interrupts, only interrupts of higher priority than the one currently executing can interrupt the current handler. I don't know how to eMail the ChipKit developers, but to make them note thi= s would be good. PS: I also have a PIC32MX3XX PIC, I will test the ipl7 vs >Cheers >Chris > >On 3 February 2012 20:53, Electron wrote: > >> At 10.50 2012.02.03, you wrote: >> > >> >> I'm not using and I don't want to use the standard library routines >> >to manage them, >> >> yet all the other <=3D6 levels work perfectly, just the 7 doesn't. Is >> >there anything >> >> special for level7 I'm missing, like a call to enable shadow set, etc= ...? >> > >> >I don't know about PIC32, but on PIC24 IIRC L7 interrupts are reserved >> >for the error trap interrupts that the CPU itself generates. Are you >> >sure you are allowed to have normal interrupt routines as L7 >> >interrupts, as this would mean the trap routines cannot work. >> >> I couldn't find anywhere anything that suggested they cannot be used, I >> indeed >> found references that they can, but they use the shadow register set. >> >> >> At 18.13 2012.02.03, you wrote: >> > >> >On Feb 2, 2012, at 10:44 AM, Electron wrote: >> > >> >> I'm not using and I don't want to use the standard library routines t= o >> manage >> >> them, yet all the other <=3D6 levels work perfectly, just the 7 >> >doesn't. Is there >> >> anything special for level7 I'm missing, like a call to enable >> >shadow set, etc..? >> > >> >So what are you using? Don't you have to do something special to make >> >sure that the alternate registers have a valid stack pointer (either >> >having a separate stack, or updating the alternate SP from the main SP >> >in the ISR)? >> > >> >Does it work if you DO use the standard library routines? >> > >> >When I was looking at it, I found the MIPS ISR preamble to be "weird." >> >(Two "general purpose" registers reserved for the ISR to trash? Really= ?) >> >> I can't find enough documentation, and "Exploring the PIC32" doesn't hel= p, >> either. >> >> K0 and K1 registers are supposed to be used by the Kernel as temporary >> registers.. >> so it may be OK. I doubt that it is a compiler bug, as (probably) RTOS d= o >> use ipl7 >> CORE_TIMER as the base of their preemptive multitasking system. >> >> But I just can't find in the docs anything that helps. >> >> Yes I tried using standard libs, I tend to disassemble them and integrat= e >> the >> juice into my own code, but in this case - to avoid risk of bugs - I >> called directly >> INTEnableSystemMultiVectoredInt() and define the INT vectors >> appropriately.. from >> ipl1 to ipl6 all works wonders, ipl7 works too but then starts to >> misbehave. >> >> Your idea that a second stack must be involved is very valid, but I just >> can't find >> anything in the docs. >> >> I hoped/hope some of You had already used ipl7 interrupts, met the probl= em >> and had >> some light to share. I'd like to have one ipl7 INT, the CORE_TIMER >> actually, as in >> this stage of my project it would really start to become useful to defer >> some jobs. >> >> Cheers, >> Mario >> >> >> >BillW >> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> >--=20 >http://www.piclist.com PIC/SX FAQ & list archive >View/change your membership options at >http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .