You may find this page useful:

http://www.chipkit.org/wiki/index.php?title=3DCore_Function_Overview

It is related to how the ChipKit uses the Core Timer but has some
interesting comments about using it in general.

Cheers
Chris

On 3 February 2012 20:53, Electron <electron2k4@infinito.it> wrote:

> At 10.50 2012.02.03, you wrote:
> >
> >> I'm not using and I don't want to use the standard library routines
> >to manage them,
> >> yet all the other <=3D6 levels work perfectly, just the 7 doesn't. Is
> >there anything
> >> special for level7 I'm missing, like a call to enable shadow set, etc.=
..?
> >
> >I don't know about PIC32, but on PIC24 IIRC L7 interrupts are reserved
> >for the error trap interrupts that the CPU itself generates. Are you
> >sure you are allowed to have normal interrupt routines as L7
> >interrupts, as this would mean the trap routines cannot work.
>
> I couldn't find anywhere anything that suggested they cannot be used, I
> indeed
> found references that they can, but they use the shadow register set.
>
>
> At 18.13 2012.02.03, you wrote:
> >
> >On Feb 2, 2012, at 10:44 AM, Electron wrote:
> >
> >> I'm not using and I don't want to use the standard library routines to
> manage
> >> them, yet all the other <=3D6 levels work perfectly, just the 7
> >doesn't. Is there
> >> anything special for level7 I'm missing, like a call to enable
> >shadow set, etc..?
> >
> >So what are you using?  Don't you have to do something special to make
> >sure that the alternate registers have a valid stack pointer (either
> >having a separate stack, or updating the alternate SP from the main SP
> >in the ISR)?
> >
> >Does it work if you DO use the standard library routines?
> >
> >When I was looking at it, I found the MIPS ISR preamble to be "weird."
> >(Two "general purpose" registers reserved for the ISR to trash?  Really?=
)
>
> I can't find enough documentation, and "Exploring the PIC32" doesn't help=
,
> either.
>
> K0 and K1 registers are supposed to be used by the Kernel as temporary
> registers..
> so it may be OK. I doubt that it is a compiler bug, as (probably) RTOS do
> use ipl7
> CORE_TIMER as the base of their preemptive multitasking system.
>
> But I just can't find in the docs anything that helps.
>
> Yes I tried using standard libs, I tend to disassemble them and integrate
> the
> juice into my own code, but in this case - to avoid risk of bugs - I
> called directly
> INTEnableSystemMultiVectoredInt() and define the INT vectors
> appropriately.. from
> ipl1 to ipl6 all works wonders, ipl7 works too but then starts to
> misbehave.
>
> Your idea that a second stack must be involved is very valid, but I just
> can't find
> anything in the docs.
>
> I hoped/hope some of You had already used ipl7 interrupts, met the proble=
m
> and had
> some light to share. I'd like to have one ipl7 INT, the CORE_TIMER
> actually, as in
> this stage of my project it would really start to become useful to defer
> some jobs.
>
> Cheers,
> Mario
>
>
> >BillW
>
> --
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.