On Feb 3, 2012, at 9:59 PM, Mark Hanchey wrote:

>> it=92s sometimes possible to share the counter/timer interrupt with an e=
xternal device, but rarely a good idea to do so.

That description pre-dates the fancier vectored interrupt controller that i=
s in the m4k cpu.  It looks like the IP vendors enhanced and included the i=
nterrupt controller (as part of the MIPS core, rather than a vendor-specifi=
c peripheral) as part of their attempts to court the embedded processor mar=
ket (it's also one of the differences between ARM7 and CM3 cores...)

BillW


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