On Feb 3, 2012, at 10:53 AM, Electron wrote:

>> When I was looking at it, I found the MIPS ISR preamble to be "weird."=20
>> (Two "general purpose" registers reserved for the ISR to trash?  Really?=
)
>=20
> I can't find enough documentation,

There is example code in the "interrupts" section of the pic32 manual.
See example 8.9 "Prologue With a Dedicated General Purpose Register Set in =
Assembly Code" in DS61108B, for example.

And there is the MIPS m4k documentation.

Also, MIPS seems to be a favorite architecture for college classes, and a g=
oogle for "MIPS K0 K1" turns up pdfs, ppts, and quite a lot of info.  It se=
ems to be a good/bad point for chips based on 3rd party cores.  On the good=
 side there is all this extra documentation.  On the bad side, the actual c=
hip vendor gets complacent about describing the details themselves in favor=
 of "use the standard code."

I went searching when chipkit was having mysterious interrupt-related hangs=
..  Starting with the disassembled code: "It's not save K0 and K1!"  Search,=
 search: "Oh, it just ... doesn't.  Wow."

It seems to me like it ought to be possible to write some really streamline=
d ISR code for MIPS.  Even without the extra register set, you've got two w=
hole registers to play with; that ought to be enough to increment a systick=
 timer...  But that doesn't seem to be what people do, and I don't see DISC=
USSION.  Sigh.

BillW

--=20
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