At 10.50 2012.02.03, you wrote:
>=20
>> I'm not using and I don't want to use the standard library routines=20
>to manage them,
>> yet all the other <=3D6 levels work perfectly, just the 7 doesn't. Is=20
>there anything
>> special for level7 I'm missing, like a call to enable shadow set, etc..?
>
>I don't know about PIC32, but on PIC24 IIRC L7 interrupts are reserved=20
>for the error trap interrupts that the CPU itself generates. Are you=20
>sure you are allowed to have normal interrupt routines as L7=20
>interrupts, as this would mean the trap routines cannot work.

I couldn't find anywhere anything that suggested they cannot be used, I ind=
eed
found references that they can, but they use the shadow register set.


At 18.13 2012.02.03, you wrote:
>
>On Feb 2, 2012, at 10:44 AM, Electron wrote:
>
>> I'm not using and I don't want to use the standard library routines to m=
anage
>> them, yet all the other <=3D6 levels work perfectly, just the 7=20
>doesn't. Is there
>> anything special for level7 I'm missing, like a call to enable=20
>shadow set, etc..?
>
>So what are you using?  Don't you have to do something special to make=20
>sure that the alternate registers have a valid stack pointer (either=20
>having a separate stack, or updating the alternate SP from the main SP=20
>in the ISR)?
>
>Does it work if you DO use the standard library routines?
>
>When I was looking at it, I found the MIPS ISR preamble to be "weird."=20
>(Two "general purpose" registers reserved for the ISR to trash?  Really?)

I can't find enough documentation, and "Exploring the PIC32" doesn't help, =
either.

K0 and K1 registers are supposed to be used by the Kernel as temporary regi=
sters..
so it may be OK. I doubt that it is a compiler bug, as (probably) RTOS do u=
se ipl7
CORE_TIMER as the base of their preemptive multitasking system.

But I just can't find in the docs anything that helps.

Yes I tried using standard libs, I tend to disassemble them and integrate t=
he
juice into my own code, but in this case - to avoid risk of bugs - I called=
 directly
INTEnableSystemMultiVectoredInt() and define the INT vectors appropriately.=
.. from
ipl1 to ipl6 all works wonders, ipl7 works too but then starts to misbehave=
..

Your idea that a second stack must be involved is very valid, but I just ca=
n't find
anything in the docs.

I hoped/hope some of You had already used ipl7 interrupts, met the problem =
and had
some light to share. I'd like to have one ipl7 INT, the CORE_TIMER actually=
, as in
this stage of my project it would really start to become useful to defer so=
me jobs.

Cheers,
Mario


>BillW

--=20
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