--_002_20111215195649835775techmanPC_
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

On Thu, 15 Dec 2011 01:03:47 -0600 (CST), bladetooth@verizon.net wrote:
:: Digikey seems to think PIC18LFK22-E/P and PIC18LFK22-I/P have
:: different maximum processing speeds, and not just different
:: temperature ranges.

This is correct, not only is there a temperature range difference, but also=
=20
a maximum frequency (don't forget higher temperature means speed must be=20
slower if cooling of some kind isn't catered for). On page 328 of the data=
=20
sheet (http://ww1.microchip.com/downloads/en/DeviceDoc/41365E.pdf), you'll=
=20
see the Voltage versus frequency graph, this states the extended version=20
has a maximum frequency of 48MHz against the standard ranges' part of 64
MHz.

::In 80437F.pdf, the errata for the PIC18LFK22, Item 4.5 mentions that,=20
::while using I2C, the RCEN bit not being cleared when an ?Improper Stop?

I haven't looked at that particular errata sheet, but the one for the 18K23=
=20
might have better grammar=20
(http://ww1.microchip.com/downloads/en/DeviceDoc/80469D.pdf), this refers=20
to 'Improper handling of a Stop event", and their explanation of this is

"8. Module: MSSP (Master I2C? mode)
In Master I2C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condition,
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches, which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop condition
and resulting stuck RCEN bit. Clear stuck 8. Module: MSSP (Master I2C?=20
mode)
In Master I2C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, then the SCL clock stream will continue
endlessly and the RCEN bit of the SSPCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condition,
then 9 additional clocks will be generated followed
by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches, which may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop condition
and resulting stuck RCEN bit. Clear stuck "

I'll leave others to think about your last two questions.

Colin


--
cdb, colin@btech-online.co.uk on 15/12/2011
=20
Web presence: www.btech-online.co.uk =20
=20
Hosted by:  www.justhost.com.au
=20
=20
This email is to be considered private if addressed to a named  individual=
=20
or Personnel Department, and public if addressed to a blog,  forum or news=
=20
article.
=20
=20
=20




--_002_20111215195649835775techmanPC_
Content-Type: text/plain; name="ATT00001.txt"
Content-Description: ATT00001.txt
Content-Disposition: attachment; filename="ATT00001.txt"; size=208;
	creation-date="Thu, 15 Dec 2011 02:04:48 GMT";
	modification-date="Thu, 15 Dec 2011 02:04:48 GMT"
Content-Transfer-Encoding: base64

LS0gDQpodHRwOi8vd3d3LnBpY2xpc3QuY29tIFBJQy9TWCBGQVEgJiBsaXN0IGFyY2hpdmUNClZp
ZXcvY2hhbmdlIHlvdXIgbWVtYmVyc2hpcCBvcHRpb25zIGF0DQpodHRwOi8vbWFpbG1hbi5taXQu
ZWR1L21haWxtYW4vbGlzdGluZm8vcGljbGlzdA0K

--_002_20111215195649835775techmanPC_--
.