> I've always been a fan of a similar design, using FETs (P + N), it invert=
s
> the signal but is VERY close to rail to rail.

That sounds like an unbuffered CMOS inverter as shown at
http://en.wikipedia.org/wiki/Inverter_%28logic_gate%29 . The trick is not
getting both FETs conducting at the same time.

Harold


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