On Mon, Nov 14, 2011 at 8:19 AM, Yigit Turgut wrote: > Hi all, > > Original hardware IC provides 480MB/s and the core provides 25MB/s. > 20MB/s is enough for me now thus I decided to give the core a go since > XC3S500E will be on the board already with %~45 unused core. > > http://opencores.org/project,ft2232hcore > > I used it as a part a design in ISE 13.2 and it seems to occupy 2 > cores (with 11inputs,+6outputs). It's a spartan . > > Anyone tried it ? I am trying to shrink it to 1 core do you think it > is worth to effort ? Also XC3S500E supports 620Mb/s per I/O, thus > achieving 480Mb/s seems to be possible to me ? > > Have a nice day. Excellent. I did not know this existed. I don't understand, what do you mean by "occupy 2 cores"? Also, what is the IO standard used for USB2.0? I know it's differential signalling, but is it LVDS? --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .