PS: sorry I forgot to specify the Wikipedia link: http://en.wikipedia.org/wiki/Cell_%28microprocessor%29#Synergistic_Processi= ng_Elements_.28SPE.29 At 18.20 2011.11.04, you wrote: >Em 4/11/2011 14:33, Ariel Rocholl escreveu: >>>> I have an old PDA I won at some "MIPS Inside" trade-show. They just >> lost out...) >> >> That is correct, my experience too. >> >> Up until year 2000, all PDAs with Microsoft OS (WinCE or PocketPC) were >> working with MIPS, SH-3 and ARM. But in 2001 MS moved to support Intel >> StrongARM only (see >> http://www.theregister.co.uk/2001/09/07/ms_pocketpc_2002_kills_hitachi/)= , >> probably because of a company agreement with Intel and having little to = do >> with technology. In any case, that moved Hitachi SH-3 and MIPS out of th= e >> picture for PDA and upcoming smartphones. >> >> I remember having to produce three different binaries to distribute in >> those MS platforms... >> >> However, MIPS32 Au1250 and Au1300 is used in lot of consumer Tablet and >> video players, it is just they no longer fight for "MIPS inside" kind of >> thing. > > >MIPS are used also in the Playstation 1 and 2 and if I remember it >right, the 7 SPEs in the PS3 (the CPU has 8 SPEs with one always disabled)= .. No, the main processor is a PowerPC while the SPE's (Synergistic Processing Elements) are custom processors. Wikipedia describes the SPE this way: Each SPE is composed of a "Synergistic Processing Unit", SPU, and a "Memory= Flow Controller", MFC (= DMA, MMU, and bus inte= rface).[31] An SPE is a RISC proce= ssor with 128-bit SIMD organization[27][32][33] for single and doub= le precision instructions. With the current generation of the Cell, each SP= E contains a 256 KiB embedded SRAM for instruction and data, called "Local Sto= rage" (not to ! be mis taken for "Local Memory" in Sony's documents that refer to the VRAM) which = is visible to the PPE and can be addressed directly by software. Each SPE c= an support up to 4 GiB of local store mem= ory. The local store does not operate like a conventional CPU cache since it is neither transparent to software no= r does it contain hardware structures that predict which data to load. The = SPEs contain a 128-bit, 128-entry register file and measures 14.5 mm2 on a 90 nm process. An SPE can opera= te on sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, = or four single-precision floating-point numbers in a single clock cycle, as= well as a memory operation. Note that the SPU cannot directly access syste= m memory; the 64-bit virtual memory addresses formed by the SPU must be pas= sed from the SPU to the SPE memory flow controller (MFC) to set up a DMA op= eration within! the s ystem address space. In one typical usage scenario, the system will load the SPEs with small pro= grams (similar to threads), chaining the SPEs together to handle each step in a complex op= eration. For instance, a set-top = box might load programs for reading a DVD, video and audio decoding, and di= splay, and the data would be passed off from SPE to SPE until finally endin= g up on the TV. Another possibility is to partition the input data set and = have several SPEs performing the same kind of operation in parallel. At 3.2= GHz, each SPE gives a theoretical 25.6 GFLOPS of single precision performance. Compared to a modern person= al computer, the relatively high overall floating point performance of a Ce= ll processor seemingly dwarfs the abilities of the SIMD unit in desktop CPU= s like the Pentium 4 and the Athlon 64. However, comparing only floati= ng point abilities of a system is a one-dimensional and application-specifi= c metric. Unlike a Cell processor, such desktop CPUs are more suited to the= general purpose software usually run on personal computers. In addition to= executing multiple instructions per clock, processors from Intel and AMD f= eature branch predictors. Th= e Cell is designed to compensate for this with compiler assistance, in whic= h prepare-to-branch instructions are created. For double-precision floating= point operations, as sometimes used in personal computers and often used i= n scientific c! omputi ng, Cell performance drops by an order of magnitude, but still reaches 20.8= GFLOPS (1.8 GFLOPS per SPE, 6.4 GFLOPS per PPE). The PowerXCell 8i variant= , which was specifically designed for double-precision, reaches 102.4 GFLOP= S in double-precision calculations.[34] Recent tests by IBM show that the SPEs can reach 98% of their theoretical p= eak performance using optimized parallel Matrix Multiplication.[28] Toshiba has developed a co-processor powered by four SPEs, but no PPE= , called the SpursEngine designed= to accelerate 3D and movie effects in consumer electronics. --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .