On Sat, 2011-10-29 at 13:07 -0400, V G wrote: > On Sat, Oct 29, 2011 at 12:40 PM, Herbert Graf > wrote: > =20 > You're right, a "normal" IO is in no way capable of switching > at > 3.125GHz using fabric. >=20 >=20 > Which makes me wonder how desktop CPUs switch at over 3GHz internally, > and 2GHz(1GHz?) on the front side bus (which is IO). Same as how the hi speed transceivers in FPGAs do it: through VERY careful design. CPUs are massively pipelined beasts, with tons of custom logic (vs. things like GPUs which tend to use the fab libraries for pretty much all logic). Since everything is set in stone when the CPU is designed paths can be optimized as much as possible for speed. In an FPGA the tradoff of near infinite logic flexibility is relatively large distances between chunks of logic. That is why the equivalent amount of logic in an FPGA uses MUCH less die area in an ASIC. You can design a transistor to switch really really fast, but if the next transistor is a fair distance away you'll only be able to run that logic at some much lower speed. TTYL --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .