I always used to wonder this, too, but I think that the answer is that internal interconnects can have FAR less capacitance than ones that have to make it out to the outside of the chip. The primary limitation on digital gate switching time is how fast the FETs can charge and discharge the parasitic capacitance which is connected to their output. A 3 mm long bond wire connected to a bond pad on one side and the output pin on the other has much more capacitance than a 10 micron-long trace within the die. Sean On Sat, Oct 29, 2011 at 1:07 PM, V G wrote: > On Sat, Oct 29, 2011 at 12:40 PM, Herbert Graf wrote: > >> You're right, a "normal" IO is in no way capable of switching at >> 3.125GHz using fabric. > > > Which makes me wonder how desktop CPUs switch at over 3GHz internally, an= d > 2GHz(1GHz?) on the front side bus (which is IO). > > >> To support high speed serial protocols like PCIE, SATA, Ethernet, etc, >> FPGAs for years have had high speed serial-parallel transceivers. Xilinx >> called theirs RocketIO (I think they are deprecating that name, I hear >> it less and less in conversation). There have been several generations, >> the V6 parts have some IOs that support serial speeds of I think >> 10-12Gbps. >> >> Again, how the fabric deals with such fantastic speeds is through >> parallelism. If you look up the GTP transceiver you'll see that it's >> high speed side is single bit differential, while it's low side speed is >> likely 10 or 20 bits wide (I'm guessing, it could be other widths >> depending how you configure the block in coregen). >> > > Thank you, that's exactly what I was wondering. > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .