On Fri, Oct 28, 2011 at 12:05 PM, Herbert Graf <hkgraf@gmail.com> wrote:

> Google "pipelining". How you do it is very design dependant, and is
> often not possible.
>
> In your case, a good example might be displaying stuff on an LED.
>
> You might have logic generating something, that then goes to a bcd-7seg
> converter. For example: put a set of flops between the logic and the
> converter, and then another set of flops (put those in the IOBs) between
> the output of the converter (which tend to be combinational logic) and
> the physical IO pins. The result is your LEDs will take 2 extra clocks
> to show the correct output, but at 200MHz your eye most certainly won't
> notice a difference. For the tool, it gives it 2 extra clock periods to
> get the output of your logic, through the converter and out to the LED
> pins.
>
> Again, this is just an example, it will likely not improve the speed of
> your design, mostly because it's pretty simple to begin with.
>
> This technique is usually the most useful when dealing with
> unidirectional data flows. A classic example is something like video.
> You take pixels in, transform them somehow, and then output them.
> Chances are your output device won't care if the outputted pixels are
> delayed a few clock ticks, so you can take advantage of that and
> pipeline your processing. Have one little block do something, then flop,
> then another block doing the next bit of processing, then flop, etc.
>
> People talking about CPUs often mention pipe-lining as a technique to
> increase speed. Even PICs use pipelining to do their stuff..
>
>
Makes sense now.


> > I was looking into this and experimenting with LVDS which can supposedl=
y
> > operate up to 666Mbit/s on the Spartan 3E. I assume it uses a parallel
> input
> > and outputs a serial stream. I searched, but couldn't find out how to u=
se
> > the LVDS module. The CoreGen has no wizard for instantiating it. How
> would I
> > make use of it? I think it has something to do with IOBUF_LVDS, but don=
't
> > know how to use it. I came up with a few application notes, but at the
> end
> > of the day, couldn't find out how to instantiate the module.
>
> There is no LVDS module (low voltage differential signalling), that's
> just a voltage standard. You set it in the IO pin configuration GUI
> (can't remember the name of the tool now, I usually do this stuff in the
> text file, don't like using the GUIs).
>
> As for the speed, IOs are an example of what I was talking about.
> Generally it's pretty much impossible you'd be able to run your fabric
> at 666MHz, so what you do is run your IOs at 333MHz in DDR mode, and
> then parallel things up so you work on your data at a lower rate.


Ah!

Looking at some app notes now. This information is hard to find.

So let's say I wanted to just send a stream of 1s and 0s via LVDS. I'd just
set the IO standard to LVDS and do this: ?

always @(posedge clk or negedge clk)
begin
    one_of_the_differential_pins <=3D !one_of_the_differential_pins;
end
--=20
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