On Fri, 2011-10-28 at 02:23 -0400, V G wrote:
> Anyway, added a period constraint and tested with both XST and Synplify.
>=20
> Synplify can give me up to ~260MHz,
> XST can give me up to ~210MHz according to the post route static timing
> reports.
>=20
> Is there anything I (as a human) can do to improve these speeds?

You can tell the synthesizer and P&R to focus on speed more then size,
there are various options on both sides for that sort of fine tuning. If
your FPGA is relatively empty I doubt you'll get much of a boost, but
you never know.

> For now, I'll just stick to 200MHz with XST.
>=20
>=20
> Synplify seems to be generating faster designs. How would I go about
> generating a bit file from the Synplify Pro IDE? I added a place and
> route implementation to the thing, but that's as far as I got.

Import the edf created by synplify into ISE and run the design there to
get to bitgen.

TTYL

--=20
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