On Thu, 2011-10-27 at 02:44 -0400, V G wrote:
> The following is true:
>=20
> - Synplify synthesis tool produces a synthesis that works the way I expec=
t
> it (what I wrote my code to do).
> - XST sometimes seems to synthesize the way I expect it, and most of the
> time not with the code above.
> - I am running at -5 speed grade which is higher performance. I was runni=
ng
> -4 before (did not notice initially), so I changed it to -5. This did not
> make any difference to the behaviour of XST.
> - In the -5 speed grade, the chip can run at up to 333MHz according to th=
e
> datasheet (I believe). My input clock (on the board) is a 50MHz oscillato=
r.
> I am instantiating a DCM to output a 300MHz clock via x6 multiplier. When=
 I
> changed it to x5 multiplier (250MHz), it XST then *seems* to work the way=
 I
> expect it to, but I'm still not sure what's going on.

Sounds like you are having timing issues, and you are either not
checking for them, or not constraining for them properly.

As for frequecy, this is NOT a PIC. The 333Mhz translates to the
switching frequency of the flops. It does NOT mean your design can run
at that speed. In fact, it's entirely likely your design won't run much
past 150MHz without some effort. The maximum frequency you can run at is
dependant on several factors. The static timing report will tell you if
your design passed timing, and what the max speed your design can run at
is.

Look up "timing constraints" in the Xilinx docs. You'd going to have to
constrain your input clock, and the output of your DCM.

TTYL




--=20
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