On Oct 27, 2011, at 6:41 AM, V G wrote: > On Thu, Oct 27, 2011 at 6:38 AM, V G wrote: >=20 >> [...] >>=20 >> Synthesizing is driving me nuts. My code seems sane, but the synthesis >> doesn't seem to reflect that. Even worse, simulation takes forever. SIGH= .. >>=20 >=20 >=20 > Edit: NOPE. Adding a BUFG doesn't seem to fully fix it. It only delays th= e > observed reset. An additional LED is allowed to light up (the next one in > the sequence), but it still resets. >=20 The tools usually put a bufg in on their own (check netlist edif or use fpg= a editor) to verify. I usually put them in the code just to be sure. MD --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .