On Oct 27, 2011, at 6:38 AM, V G wrote: >=20 > Synthesizing is driving me nuts. My code seems sane, but the synthesis > doesn't seem to reflect that. Even worse, simulation takes forever. SIGH. Speed up the counter timeout for simulation. We do this all the time. This = assumes your bug is not in the counter itself. That said your next option is to simulate your post synthesis netlist. Or e= ven better the post place and route netlist with timing included (sdf). Use= "netgen" (xilinx) to get your netlist.=20 MD --=20 http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .