On Thu, Oct 27, 2011 at 2:44 AM, V G <x.solarwind.x@gmail.com> wrote:

> [...]
> The following is true:
>
> [...]
> - In the -5 speed grade, the chip can run at up to 333MHz according to th=
e
> datasheet (I believe). My input clock (on the board) is a 50MHz oscillato=
r.
> I am instantiating a DCM to output a 300MHz clock via x6 multiplier. When=
 I
> changed it to x5 multiplier (250MHz), it XST then *seems* to work the way=
 I
> expect it to, but I'm still not sure what's going on.
> [...]
>


I randomly decided to add a global BUFG to my code and it *seems* to have
fixed the observed problem of premature "resetting".

This is what I did (non-relevant code removed):

module main(clk, count, Led, seg, an);

input wire clk;
output reg [39:0] count =3D 0;
[...]

wire clkout2;

clk0 clock(
..CLKIN_IN(clk),
..CLKFX_OUT(clkout)
);

BUFG  b1(
..I(clkout),
..O(clkout2)
);



I simply buffered the output of the DCM with a global buffer and then took
that signal as the final clock. I have NO idea why, but this *seems* to hav=
e
fixed the observed problem. However, there may be some other issues going o=
n
that I can't observe. I still don't know what the problem is and why adding
a BUFG seems to have fixed it. Emphasis on SEEMS to have "FIXED" the
"PROBLEM" since I really have no idea what the hell is going on with XST.

In other news, Synplify seems to be driving pins that are not even in the
design (decimal point LED seems to synchronously flash with the change of a
certain digit even though the pin is not even routed anywhere in the
design).

Synthesizing is driving me nuts. My code seems sane, but the synthesis
doesn't seem to reflect that. Even worse, simulation takes forever. SIGH.
--=20
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