I wrote a very simply 4 digit 7-segment multiplexed LED display counter in
Verilog.

Code:

`timescale 1ns / 1ps

module main(clk, Led, seg, an);

input wire clk;
output wire [7:0] Led;
output wire [6:0] seg;
output wire [3:0] an;

wire clkout;

clk0 clock(
..CLKIN_IN(clk),
 .CLKFX_OUT(clkout)
);

reg [39:0] count;

assign Led[7:0] =3D count[31:24];

always @(posedge clkout)
begin
count =3D count + 1;
end

wire [3:0] rDigit;

sseg digit0(
 .ssOut(seg[6:0]),
..nIn(rDigit)
);

display_mux display(
 .an_select(count[16:15]),
..data(count[39:24]),
..digit(rDigit),
 .an(an[3:0])
);

endmodule



module display_mux(an_select, data, digit, an);
input wire [1:0] an_select;
input wire [15:0] data;
output reg [3:0] digit;
output reg [3:0] an;

always @(an_select)
begin
case(an_select[1:0])
 2'b00: begin an[3:0] <=3D 4'b1110; digit <=3D data[3:0]; end
2'b01: begin an[3:0] <=3D 4'b1101; digit <=3D data[7:4]; end
 2'b10: begin an[3:0] <=3D 4'b1011; digit <=3D data[11:8]; end
2'b11: begin an[3:0] <=3D 4'b0111; digit <=3D data[15:12]; end
 default: begin an[3:0] <=3D 4'b0000; digit <=3D 0; end
endcase
end
endmodule






What it does is simply count up a 40 bit register (count) and
display count[31:24] on 7 LEDs and count[39:24] on the 4 digit 7-segment
display.

When I synthesize with XST, (even with the 7-segment display module
disabled, so it just shows the 7 LEDs), the last two LEDs don't light up,
and I think count[39:29] isn't even being incremented. When I synthesize
with Snyplify Pro, everything works as expected. I'd rather use XST because
the error messages are much, much easier to understand.
--=20
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