On Tue, 2011-10-25 at 17:27 -0400, V G wrote:
> > FWIW, I wouldn't use coregen to instantiate BRAMs. Just write verilog
> > that infers a memory and let the tool sort out BRAM usage. The added
> > benefit is your design won't be locked to one particular family, or
> > vendor, and if you parametrize things you will be able to change the
> > size of your memory in the future with just changing a few constants.
> >
> >
> Do you recommend just a plain register array? Or anything specific for th=
at?

Yes. Added benefit is it makes your code MUCH more readable since the
person doesn't have to know what a "BRAM" is.

In fact, I try as hard as possible to ensure all verilog I write is as
platform independent as possible. That way, I can change
tools/vendors/sims with VERY little change.=20

Obviously some things pretty much have to be specific to a part (i.e.
DCMs are not interchangeable between even Xilinx families, but you have
to use them to get your clocking correct, I generally wrap them in a
"clock block" so that most of my code remains the same, I just have to
change the clock block when needed (i.e. when using a SIM where I don't
have a Xilinx primitive cell library)).

TTYL



--=20
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.